1. Field of the Invention
This invention relates to the field of data processing systems. More particularly the invention relates to interconnect blocks for data processing apparatus, the interconnect blocks providing data routes via which one or more initiator devices such as a master may access one or more recipient devices such as a slave.
2. Description of the Prior Art
There are a number of different ways to interconnect devices on a data processing apparatus such as a system-on-chip (SoC).
These basically fall into two different systems, circuit-switched systems and packet switched systems. Each of these systems have their own advantages and disadvantages.
When the number of nodes (ie. masters and slaves) to be connected becomes large, fully connected circuit-switched interconnects such as ARM®'s PL300 tend to suffer from a large increase in area and a reduction in maximum clocking frequency.
For these reasons hierarchical circuit switched interconnect structures are often used in SoCs. FIG. 1a shows a fully connected circuit switched interconnect 10 according to the prior art, while FIG. 1b shows one divided into two hierarchical portions 20, 30. The device of FIG. 1b provides an improvement in area over the device of FIG. 1a of 25% and an improvement in overall frequency of 24%.
The interconnect of FIG. 1b provides an improvement in area and operating frequency at a cost of reduced connectivity when compared to the interconnect of FIG. 1a. The reduced connectivity comes from the masters connected to portion 30 not being able to access the slaves connected to portion 20 in this embodiment. A further problem with the hierarchical circuit-switched interconnect structure of FIG. 1b is that traffic between portions 20 and 30 must share a common route and thus, if there is contention for this route performance of the interconnect as a whole is reduced. A case where this contention results in particularly poor performance is when a connection between a master and a slow slave is made across this connection. This blocks any other master connected to portion 20 from communicating with a slave connected to portion 30.
This problem can be particularly significant in a “blocking” protocol such as AMBA 3 AXI, that is a protocol in which a transfer, once initiated, cannot be removed until it completes.
In packet-switched systems, a packet of data can be sent independently of other packets of data from the same transaction and can thus, be sent down a route that is available at that time. This means that a particular route is only blocked for the length of time it takes to send the packet. This is advantageous when compared to circuit-switched systems where generally a whole transaction must be sent down one route and thus, this route is blocked until the transaction has completed, or in some systems has been removed.
Grouped adaptive routing is a technique that is used in packet switched networks and which is described by Reinemo et al. in “Topologies and Routing in Gigabit Switching Fabrics” a scientific thesis from The University of Oslo 2000. It is described as a technique that enables a packet to take one of several paths through a network depending on the local states of contention, by allowing the packet to be sent down any link in the group which is not currently in use. It has been used in star topologies using worm-hole packet-switched routers.
SGS-Thomson Microelectronics “STC104 asynchronous packet switch” engineering data 1996 discloses a switch that implements grouped adaptive routine so that consecutive output links are grouped to allow packets routed to the first link of the group to be sent down any free link in the group depending on which is the first link to become available.
However, despite the advantages of not blocking a route circuit-switched networks are currently preferred over packet switched systems for System-on-Chip interconnects, see for example “NOC, NOC, NOCing on heaven's door beyond MPSCOS”, report on 7th Annual Symposium on System-on-Chip”, EDN Dec. 8, 2005. This is because they can be simple, low-latency, low-power and low-area compared to packet-switched architectures. This is in part because they do not require network buffers or complex switches.
Embodiments of the present invention seek to improve the performance of hierarchical circuit switched interconnects without overly increasing chip resources.